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That is, data received from the frontend LAN by the node of the backbone LAN is divided in a plurality of fixed length data units. However, only one of the data units of the backbone LAN include the routing information, and other nodes of the backbone LAN does not recognize data to be learned.

Also in the prior art, since learning the routing information of a backbone LAN constituted by a plurality of physical or logical links is not considered, the following point becomes a problem.

When the node receiving the frame of the frontend LAN performs transmission by broadcast to the backbone LAN, the same data is transmitted along all links. On the other hand, as the learning manner in other node, the learning must be performed from all links. In this case, the learning by the same information occurs in the number of the links, and the futile learning process increases.

Also in the prior art, since learning of the routing information of a network constituted by a loop-shaped link is not considered, following point becomes a problem. That is, the node forwarding data again receives the data after taking a round of the loop. Consequently, the learning is performed twice, i. In addition, the prior art relating to a bridge circuit is disclosed, for example, in U.

An object of the invention is to provide a bridge apparatus for connecting a network performing communication in fixed length data unit to other network and a control method thereof. Another object of the invention is to provide a bridge apparatus for connecting a network constituted by a plurality of links to other plural networks and a control method thereof.

A further object of the invention is to provide a bridge apparatus for connecting a network constituted by a loop-shaped link to other network and a control method thereof.

Still another object of the invention is to provide a bridge apparatus for connecting a plurality of frontend networks connecting stations to a backbone network and a communication system between networks using the bridge apparatus.

In order to attain the foregoing objects, in the invention, in constitution that frontend LANs connecting a plurality of stations are connected respectively to a plurality of nodes of a backbone LAN constituted by a plurality of physical or logical links. Each node corresponds to a frontend LAN.

A first data long data block received from the frontend LAN is divided and converted into one or plural second data short data block units with fixed length and then transferred to a destination node.

A bridge apparatus is provided where the transferred second data blocks are combined and converted into the first data block. The bridge apparatus can transmit the second data blocks to arbitrary links, and the second data blocks are received from one link. The bridge apparatus also has means for deciding whether the learning of routing information should be performed or not, based on the learning indication information existing in the second data blocks including the routing station position information.

That is, in the invention, a bridge apparatus is provided where a first data block received from a frontend LAN is divided and converted into one or more second data blocks having fixed length and error check code and then transferred to a destination node. The bridge apparatus has means for supplying the information indicating whether the learning is necessary or not learning indication information to the second data block including the routing information among the second data blocks, and means for learning the routing information based on the information indicating whether the learning is necessary or not when the second data blocks are received.

That is, the basic principle of the invention is in that the data transfer can be performed between a plurality of frontend LANs through a backbone LAN constituted by a plurality of loop shaped physical or logical links.

The data is segmented to short data units with fixed lengths a. In the invention, in a backbone LAN system comprising a plurality of loop-shaped physical or logical links and a node device connected thereto for transferring data to second data units with fixed length, each node has a plurality of ports corresponding to frontend LANs and each port has the bridge function to perform the data transfer between a plurality of physical or logical links of the backbone LAN and the frontend LANs.

The node at the transmission side supplies the learning indication to the short data including the routing information, and the node or port at the receiving side performs the learning of routing information from the learning indication of the short data. On receiving the first data from the frontend LAN, the port registers set sending station address of data and the self node address go and the self port address to the entry of the entry table, and uses the destination address of the data as a key retrieve the entry.

The decision results are of the following three sorts. Consequently, the data is discarded. The port and the receiving link are preferably connected fixedly. That is, the receiving port address and the receiving link have the same number, thereby at the transmission side the data is transmitted to the link having the same number as that of the destination port address, and at the receiving side the receiving may be performed only from the link to which the self port is connected.

In this case, the entry need not be retrieved using the destination station address as a key. The port, after transmission of the short data with the learning indication, is not learned here, because the short data performing one round of the loop has been previously learned at the receiving state from the frontend LAN.

The node takes the short data with the learning indication bundled in all links, and transmits the sending station information to all ports in the self node. Each port registers the sending station information to the entry possessed by the port respectively.

At the transmission side transmission port , the learning indication is added to the short data indicating the sending station position. The short data with the learning indication is then transmitted only to one link. Even in broadcast, only one arbitrary link is sufficient for the short data including the sending station address requiring the learning indication for example, the link corresponding to the self port.

Also the invention may be learned as follows. Even in the case of discard, only the short data including the position information of the sending station may be transferred to the frontend LAN. Thereby, all ports can register the station position to the entry in similar manner to the case of forwarding. Thereby transmission by broadcast due to the unknown destination is decreased. Embodiments of the invention will now be described referring to the accompanying drawings.

A backbone LAN 0 comprises a loop-shaped physical link 13 and a plurality of nodes 10 connected thereto. To each frontend LAN 25 are generally connected a plurality of stations also called terminals A management device may use a general work station having a file device.

A node with the management device connected thereto is called a master node, and a node other than this is called a slave node. The management device is connected to the master node through a LAN, for example, a Ethernet The management device has the operation command function, that is, the function of changing the configuration of the backbone LAN in accordance with the command inputted by the operator and collecting the statistical information within the node.

It also has the status monitor function, that is, the function of supervising the operation state of the backbone LAN and generating the alarm for the operator upon detecting trouble and also performing the logging for the file device. In FIG. The node 10 comprises a loop access controller and a plurality of ports 10A. Furthermore, the loop access controller is connected to all the ports 10A through the line L commonly.

The relevant invention regarding the node constitution assigned to the same assignee as that of the present application is disclosed in Y. Takiyasu et al. Further, numeral designates a microprocessor. The microprocessor can access the memory A and other members within the loop access controller and also the Ethernet interface if any.

Further the control information is transmitted or received from the microprocessor through the switch means , thereby communication is possible between the microprocessors with different nodes The port 10A comprises a receive controller where cells received from the switch means are assembled into a frame of the frontend LANs, a re-assemble buffer , a transmit controller , a cell buffer where frames of the frontend LANs are divided into cells and transmitted in cell unit to the switch means , an FDB Filtering Data Base controller , and a frontend LAN controller The frontend LAN controller further comprises an FDDI access means , a receive buffer controller , serial interfaces and , and a receive buffer Ramakrishman and Bill Hawe, Jun.

On the other hand, FIG. Although the node address and the port address are separated in the embodiment in Table 2, it is easily analogized that the node address and the port address as a whole can be treated as one node address.

In this case, in FIG. Also in another embodiment, transfer including the FCS is performed. The amount of Lf is different, but the following description can be similarly applied.

Depending on the amount of Lf, in following conditions, segment to cell generation of cell is performed, and a part or the whole of the frontend LAN frame is copied to the cell content field. In this case, the length of the cell content field is made to Lc bytes. It is usually made to several tens bytes.

Regarding only the Single cell and the First cell, the forwarding function header exists at the tip end portion of the cell content field As clearly understood from the above description, the destination station address and the source station address of the frontend LAN frame are stored in the cell content field of the First cell or the Single cell. The forward function header will be described later. The microprocessor of the loop access controller starts the operation by reset of the power ON or the like, and by the program control on the memory A comprising ROM and RAM.

Thereby, the node can communicate with other node through the physical link Thereby, the data transfer can be performed between the frontend LAN 25 and the loop access controller With the initialization of the frontend LAN controller , all frontend LAN frames transmitted by the terminal of the frontend LAN 25 can be received by receive buffer As a result, the preparation of the communication between the frontend LANs 25 through the backbone LAN network 0 is finished.

The program initialization data on the memories A and may be previously stored in the ROM, or the program initialization data from the management device through the microprocessor of the master node may be subjected to the down line load to the memory A. An embodiment of the node 10 will now be described. In following description, prefix S before each numeral refers to elements in the flow chart.

First, in order to supervise the receive of the frontend LAN frame from the frontend LAN 25 to the receive buffer , the microprocessor reads the receive buffer controller at S10, and decides the receive status of the frontend LAN frame.

If no receive, S10 is repeated. If a receive exists, to check the receiving status of the frontend LAN frame, the receive error status is decided at S If any error exists, to remove the frontend LAN frame from the receive buffer , the top frame remove command is written to the receive buffer controller at S80, and then the process goes to S If no error exists, the length of the frontend LAN frame is read from the receive buffer controller at S The SMT frame copied to the memory may be processed by other program at the microprocessor Then the FDB means , the transmission controller and the cell buffer perform the filtering, the learning, the forwarding called in the learning bridge, which shall be described later.

In the order to check whether the upward transfer is finished or not, the decision of the upward transfer finishing status REG C is performed at S If not yet finished, S60 is repeated. If it is finished, since a part of the frontend LAN frame may remain in the receive buffer , the remained length REG D is read at S70, and the buffer freed length is calculated using the frontend LAN frame length read at S The buffer freed length is set to the receive buffer controller at S75 and the buffer freed command is written so that the receive decision of next frontend LAN frame can be performed at S Next, referring to FIGS.

At the same time, the transfer command is issued to the write pointer controller , which outputs the write address and control signal to the cell buffer , thereby the frontend LAN frame is divided, for example, in four byte unit, and transferred repeatedly from the receive buffer to the cell buffer Then in the receive buffer , the buffer area corresponding to the transfer is freed by the receive buffer controller Further the transmission transfer controller makes the key address REG take the destination station address in the timing of the destination station address transferred to the cell buffer The filtering request to the FDB means is then issued on "e" line.

Also the source station address is taken by the key address REG at different timing. The three sets of address information terminal or station address, node address, port address are finished, and then the learning request is issued to the FDB means That is, the step piece number of the cell buffer may be three or more. For example, when four steps pieces of the cell buffer are provided, the following state may be assumed. An example of the content of the first step at the front column follows.

The cell is being transferred to the switch , and since the cell of the second step is finished in the filtering finish of the header generating and the result is the forward, the transfer to the switch means is suspended. Further, if the content of the third step is being filtered including the header being generated , in the content of the fourth step, the next data may be learned during the transfer and the filtering may be prepared.

As described above, since concurrent processing can be performed, even if the transfer of the cell at the first step to the switch is delayed for a long time, as long as the empty exists at the succeeding step, this area may be utilized. Thereby the filtering of the succeeding frontend LAN frame can be performed continuously and the filtering performance is improved.

That is, as long as the discard continues, the overlaying to the position is performed and therefore the empty is not lost.

The control of the cell buffer is performed by the read pointer controller and the write pointer controller in the FIFO method. The priority highest in the filtering request is 1 , followed by 2, 3, 4. Thereby, the filtering and forwarding performance of the port 10A bridge to the frontend LAN frame can be improved. As a result, it follows that:. If the result of the filtering is settled, the FDB arbitrator informs the finishing to the request source.

If three sets coincident therewith are found Found state , the values of the source node address and the source port address among the three-set address information of the write REG are set overlaid to the node address and the port address of the entry. In the Not Found state, the unused entry is searched, and values of the three-set address information of the write REG are registered to the entry.

An embodiment of the transmission controller and the cell buffer after the filtering request to the FDB means in the upward forwarding will be described. The three sets coincident with the destination station address can not be found in the FDB means The algorithm regarding calculation of values of PSN, LSN and detection of the transfer finishing is shown as follows.

If a total length Lt of adding a length Lr of a forwarding function header and a length designated by the length register is equal to or shorter than a length L c of the cell content field. For the next cell, if the new Lt is longer than the Lc,. This process is repeated, and when the new Lt finally becomes equal and shorter than the Lc.

The microprocessor performs the initial setting to the transmission cell broadcast address REG In embodiment a , the value for the simultaneous broadcast address is all "1", and it is intended that the cell is received by all 10A ports. The system application example of these embodiments will be described later. An SEQ generator is constituted by an incrementor, a NAND circuit and the like, and generates a sequence number using any algorithm in the next embodiment. An ICS generator inputs the transfer data from the receive buffer , and also inputs values of the backbone MAC header and the forward function header.

According to the transfer data input notice and the cell generation notice from the transmission transfer controller , the error check code is generated for the cell content field including the backbone MAC header, the forward function header only at the First or Single cell.

Then the ICS generator is reset in response to the reset command from the transmission transfer controller The ICS generator repeats the above operation at every cell generation notice.

The header values thus generated are stored in a cell header field REG , and then stored to each field of a corresponding cell of the cell buffer The value generated in the cell header generator and a part of the transfer frontend LAN frame from the receive buffer are stored in cell form within the cell buffer in accordance with the address assignment of the write pointer controller The cell buffer can store a plurality of for example, four pieces cells.

The read pointer controller compares the write pointer value from the write pointer controller with the self read pointer value, thereby the controller can know whether the cell buffer is "Not empty" One or more cells exist and inform the switch means of the cell transmission request. The read pointer controller and the write pointer controller are initialized by the reset of the power ON or the like, and the cell buffer becomes empty.

Next is the case when the three sets coincident with the destination station address exist in the FDB means In the case when coincident, the station assigned by the destination station address exists on the frontend LAN 25 to which the port 10A is connected, and the transfer frontend LAN frame should be discarded.

The difference between the value of the length REG A set at the transmission starting state and the frame length of the transfer frontend LAN transferred before the transfer interruption is stored in the remained length REG D. The generation cancel is provided to the write pointer controller , and a part of the cell being generated in the cell buffer is erased, and further the generation cancel is provided to the cell header generator and the update of the SEQ generator is suppressed.

Because the generation cancel notice is performed before the generation finishing of the First cell or the Single cell, a part or the whole of the transfer frontend LAN frame to be discarded is not transmitted as the cell to the switch means In the case when not coincident, the station assigned by the destination station address exists on the frontend LAN 25 to which a port 10A other than the above-mentioned port 10A is connected, and the transfer frontend LAN frame should be forwarded to the backbone LAN side.

Subsequent operation is similar to the operation described in 4. The switch means comprises a highway selector , a learning cell multiplexer , and highway processors i --l corresponding to highways i, j, k, l.

Access system of the switch means is based on so-called slotted ring system, and is an extended system to enable access of a plurality of highways. An individual port is abbreviated, for example, as a port-i 10A i. The ports-x 10A x and the highway selector are connected by lines designated TC, which T corresponding to the ports.

A port-j 10A j will now be described. The other ports act similarly. If the value is "1", representing a simultaneous broadcast address a or a group broadcast address, transfer to the cell buffers of all highways is performed.

In this case, if the cell buffer of the destination highway is full, the transfer to the cell buffer is delayed until an empty space is produced in the cell buffer. However, if the cell buffer is full, the transfer is delayed until an empty space is produced in the cell buffer.

Consequently, for the next cell transmission request from the port-j 10A j , the highway selector delays the notice of the transmission allowance to the read pointer controller As a result, the cell in accordance with the transmission request remains in the cell buffer The highway selector repeats the above operation every time the cell transmission request is received.

When the cell buffer is empty, the transmission selector forwards the cell jY as it is from the receive register to the multiplexer , as long as the cell removing request jb does not come from the receive decision means Next, the receiving of the cell will be described. When a cell corresponding to one cell of the highway j is stored to the receive register by a cell boundary signal of the highway j and the cell data input through the demultiplexer , the receive decision means is informed of the cell receiving.

When both are coincident, the transmission selector is informed of the cell removing request jb. In the transmission selector receiving the cell removing request jb, the value of B of the ACF of the cell transferred from the receive register , after a definite time, is made "0" emptying the cell. The cell is transferred from the receive register to the transmission selector and to the learning cell multiplexer , and further transferred by the R line, to the receive controller of the port-j 10A j.

As described above, the port 10A can perform the cell receiving through the R line from only the specific highway. For example, the port-k 10A k can perform the receiving from only the highway k. The learning cell multiplexer includes learning judgement means corresponding to highways, and a multiplex means Each learning judgement means includes a learning decision means , a cell buffer , and three-set address FIFO buffer A cell from the receive register of the highway is stored to the cell buffer Upon receiving the cell boundary signal and notice regarding absence of the HCS error from the receive decision means , the learning decision means , having an ICS checker circuit of an ICS with a cell content field and a backbone MAC header being error-checked, performs a decision regarding the following three conditions.

Only when all three conditions are satisfied, as shown in FIG. This storage is performed only when an empty space exists in the three-set address buffer A cell in the cell buffer not satisfying the three conditions is overlaid by the next received cell. It is easily analogized that, in place of deciding the three conditions 1, 2, 3, other embodiment of deciding the two conditions 1, 3 excluding 2 can be realized in similar manner to the above description.

The learning judgement means corresponding to other highways repeat a similar operation. The multiplex means takes the three-set address information from the three-set address buffer of i, j, k, l, for example, in the order of i, j, k, l, i, j, , and transmits the information together with the learning request notice to the L line.

As a result, the three-set address information from all highways can be commonly learned by the FDB means of all 10A ports. If the three-set address information does not exist in the three-set address buffer , the learning request is not transmitted to the L line. The learning decision means performs the write pointer control and the read pointer control for the three-set address buffer thereby performing the FIFO control of the three-set address buffer Next, returning to the port 10A, the operation of the receive controller and the re-assemble buffer will be described referring to FIG.

The transfer at the R line is repeated, for example, in units of 16 bits. If any HCS error exists, the received cell is ignored and next cell is received. The error check, detecting bit error, is performed using the ICS If any ICS error exists, the received cell is ignored and next cell is received.

Among following conditions. It is easily analogized that the group address REG is not limited to one in number, but a plurality of the registers may be provided and the different group address values are initialized thereby the cells corresponding to plural sorts of the group address can be received.

If any of 1, 2, 3 is not satisfied, the chain management means is informed of the address non-coincidence, and the informed chain management means ignores the received cell. Value 0 or 1 of the learning mode REG C is previously initialized by the microprocessor If any ICS error exists, the learning decision means is informed of the unpermissibleness of learning. The receive decision means has a circuit for performing decision and an ICS error check as above described.

As a result, the FDB means learns the three-set source address information station address, node address, port address stored in the address information REG If no error is found and the assembling of the transfer frontend LAN frame is finished Single cell or Last cell received , the chain management means informs the receive transfer controller of the receive finishing. The re-assemble buffer is a so-called three-port buffer memory, and can be accessed concurrently by the chain management means , the receive transfer controller and the FDDI access means During the data transfer from the SHIFT to the re-assemble buffer , the chain management means suppresses its own access to the re-assemble buffer The re-assemble management table in FIG.

The management entry corresponding to the port 10A of the source includes a first bucket pointer , a last bucket pointer for chaining a container called a bucket to store cells, a preceding PSN , a preceding SEQ for storing the cell values of PSN and SEQ previously received from the source port.

The bucket includes a chain pointer for chaining the bucket itself, and a cell storing means The cell storing means has both embodiments for both storing and not storing the ACF. Both have no difference in following description. A transfer frame number counter and a transfer byte number counter count the transfer frontend LAN frame number, transferred from the re-assemble buffer to the FDDI access controller, and the total byte number of these frames.

The bucket is connected to the re-assemble management table or the empty bucket entry of the re-assembled frame entry depending on the respective cases. In following description, data structure composed of a pair of first some pointers, a last some pointer and a bucket group chained by these pointers for realizing the FIFO manner is called queue.

The re-assemble buffer is initialized by the microprocessor as follows. This method is shown in the SEQ error determining tables Tables , , corresponding to the SEQ generators a - c described in 4. The chain management means performs the error check, and then performs processing shown in post-conditioning of each table. When the PSN error or the SEQ error is detected, the chain management means does not transfer the received cell to the re-assemble buffer If the received cell is a Single cell, it is connected to the re-assembled frame queue.

Otherwise the bucket storing received cell is connected to the bucket queue of the management entry ENT t. If the received cell is a last cell then all the buckets, between the bucket incorporating the First cell chained to the bucket queue through the bucket incorporating the Last cell, are connected in the order of the chain as it is to the re-assembled frame queue.

Whenever the bucket is connected to the re-assembled frame queue by receiving the Single cell or the Last cell, the chain management means notices the receive finishing sent to the receive transfer controller Further, the preceding PSN of the corresponding management entry is made single, and the first bucket pointer and the last bucket pointer are made 0.

The chain management means repeats the above-mentioned operation on each received cell. On receiving the receive finishing notice, the receive transfer controller informs the receive frame status B of the finishing notice presence.

In S, the receive frame status B decides whether the re-assembled transfer frontend LAN frame exists in the reassemble buffer If it is not received, S is repeated.

Then in order to confirm whether the transfer to the frontend LAN 25 is finished, the downward transfer finish status is decided in S If it is not finished, the S is repeated. If it is finished, process goes to S so that the presence of next transfer frontend LAN frame can be decided.

If the token goes round on the frontend LAN 25 and the FDDI access means receiving the transmission request picks up the token, notice of the transmission ready is returned from the FDDI access means to the receive transfer controller Then the receive transfer controller takes only the hatched portion of each cell on FIG.

In accordance with values of PSN and LSN of the cell, the address and length within the cell to be started in the transfer are known, and the length is added to the transfer byte number counter and the net data the hatched portion in FIG. When the transfer in the bucket is finished, the receive transfer controller takes the bucket from the re-assembled frame queue and connects it to the empty bucket queue.

If the PSN of the cell of the bucket is Next cell or First cell, the chain pointer of the bucket is followed and the next bucket is obtained, and the above operation is performed again. If the PSN thereof is Single cell or Last cell, it is recognized that the transfer of one transfer frontend LAN frame is finished, and a "1" is added to the transfer frame number counter. Consequently, every time the transfer of one transfer frontend LAN is finished, the receive transfer controller searches the re-assembled frame queue.

If nothing is found in the re-assembled frame queue, the change from finishing status to the downward transfer finish status is noticed and a series of processing is finished, and the next starting signal from the transmission start REG is awaited. On the other hand, it the re-assembled transfer frontend LAN frame to be transmitted next exists, the operation similar to 4 is repeated.

If the token holding time is over, the FDDI access means releases the token and notices the receive controller of the token release. On receiving the notice, the receive transfer controller does not perform new DMA transfer and notices the change from finishing status to the downward transfer finish status, even if the re-assembled transfer frontend LAN frame to be transmitted next exists in the re-assembled frame queue. On the other hand, if the re-assembled transfer frontend LAN frame to be transmitted is over before the token holding time is over, the receive transfer controller notices the token release command sent to the FDDI access means, and also notices the change from the finishing status to the downward transfer finish status.

The FDDI access means releases the token. The operation from setting of the transmission start REG until the notice of the finishing to the downward transfer finish status has been described. As shown in 1. Therefore, make sure that you follow these steps carefully. For added protection, back up the registry before you modify it. Then, you can restore the registry if a problem occurs. For more information about how to back up and restore the registry, see How to back up and restore the registry in Windows.

This setting is not present in the registry by default. Start Registry Editor Regedt On the Edit menu, click Add Value , and then add the following information:. The TcpMaxDataRetransmissions parameter controls the number of times TCP retransmits an individual data segment non-connect segment before ending the connection.

The retransmission timeout is doubled with each successive retransmission on a connection. It is reset when responses resume. The base timeout value is dynamically determined by the measured round-trip time on the connection. The default value for this registry entry is 5; double this value to 10 Decimal see step 2 above.

If connection timeouts still occur, try doubling the value again to 20 Decimal. This registry entry may only reduce the number of connection timeout errors that occur.

Changes to your Internet connection or router may have to be made to completely resolve the problem.

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